Fermi-FET transistor technology can lead to significant improvement in circuit performance, layout density, power requirements, and manufacturing cost with only a moderate alteration of traditional MOSFET manufacturing technology. This technology makes use of a subtle optimization of traditional buried channel technology to overcome the known shortcomings of buried channel while maintaining large improvements in channel mobility. This technology merges the mobility and low drain current leakage of BCA devices as well as the higher short channel effect immunity of SCI devices. This paper highlights aspects of the technology in a non-mathematical presentation to give a sound general understanding of why the technology is the most promising avenue for advanced very short devices.
Fermi-FET can optimize both the N-Channel and P-Channel devices with a single gate material, provided the work function is near the mid-range between N and P-type polysilicon. Materials that have been used in MOSFET technology with a suitable work function include Tungsten, Tungsten Silicide, Nickel, Cobalt, Cobalt Silicide, P-type Ge:Si and many others. There is about a 30% reduction in junction capacitance relative to traditional MOSFET devices. This fact alone gives a significant speed advantage to the Fermi-FET in large scale circuits. The total speed improvement produced by both the lowered threshold and lowered gate and junction capacitances is very substantial.
In order to illustrate the impact of lowered threshold voltages via work function engineering, the large-signal transient response of two inverter structures was simulated. A comparison of conventional CMOS and metal-gate Fermi-FET structures was performed. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET. The different delay characteristics are evident. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET.
The individual device DC characteristics were already well-known from the device simulations. For each inverter, the supply voltage was ramped up to Vd with a delay sufficient to allow the circuit nodes to settle to their initial DC state with the input low. The input was then pulsed high, then low; again with a delay time long enough to guarantee all nodes reach steady state. The corresponding outputs obtained give a comprehensive view of the device performance as compared to the traditional technology and thus acts a primary assessment of the feasibility of the new technology in lieu of existing ones.
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